1. Field of the Invention
The present invention relates to a fabrication method for a thin film field effect transistor array, and more particularly to a fabrication method for a thin film field effect transistor array suitable for active matrix liquid crystal displays.
2. Description of the Related Art
Liquid crystal displays are drawing attention as flat panel displays for portable computers and wall type televisions. In particular, the active matrix system which utilizes arrayed thin film field effect transistors formed on a glass substrate as switches for the respective pixels is expected to be applicable to televisions because of its full color display capability, and is under active development. One of the important tasks for establishing the practicability of the active matrix liquid crystal display is the cost reduction which results from the simplification of the structure and the device fabrication process. In the inversed staggered structure in which the gate electrode of the thin film field effect transistor is formed closer to the glass substrate than the source and drain electrodes, there has been disclosed a fabrication method which makes use of three sheets of photo-mask (see for example, Japanese Patent Laid Open No. 62-286271) as the prior art.
FIG. 1(a) to FIG. 1(g) show the step diagrams for forming a thin film field effect transistor element array based on the prior art method in which FIG. 1(a), FIG. 1(c), and FIG. 1(e) are plan views as seen from the top, and FIG. 1(b), FIG. 1(d), FIG. 1(f), and FIG. 1(g) are sectional views taken along the lines A--A', B--B', C--C', and D--D' in FIG. 1(a), FIG. 1(c), and FIG. 1(e). Referring to FIGS. 1(a) and 1(b), first, an indium-tin-oxide (ITO) film and a first chromium film are deposited in this order. Then, chromium gate electrodes 2a, chromium pixel electrodes 6a, transparent gate electrodes 2b, and transparent pixel electrodes 6b are formed by a photolithography method using a first photo-mask pattern. Next, referring to FIGS. 1(c) and 1(d), an SiN.sub.x film 7, an a-Si:H (hydrogenated amorphous silicon) film 8, and an n.sup.+ -a-Si:H film 9 are sequentially laminated, and portions of the SiN.sub.x film 7, the a-Si:H film 8, and the n.sup.+ -a-Si:H film 9 are removed by a photolithography method using a second photo-mask pattern except for the laminated film in the proximity of regions where thin film field effect transistors and chromium drain bus lines are to be formed. Then referring to FIGS. 1(e), 1(f), and 1(g), after forming a second chromium film, chromium drain bus lines 5a, drain electrodes 4, and source electrodes 14 are formed by a photolithography method using a third photo-mask pattern by etching the second chromium film. Then, the chromium pixel electrodes 6a consisting of the first chromium film formed on the transparent pixel electrodes 6b are removed by further etching. Simultaneously, the chromium gate electrodes 2a consisting of the first chromium film formed on the transparent gate electrodes 2b are also removed except for the portion where the chromium gate electrodes 2a cross the thin film transistors 10 and the chromium drain bus lines 5a. Next, channel parts of the thin film field effect transistors 10 are formed by removing the n-type amorphous silicon in the portions between the drain electrodes 4 and the source electrodes 14 by means of etching of the n.sup.+ -a-Si:H film 9 using the same resist pattern as in the above. It should be noted in this case that the gate bus line 3 has a laminated structure of the first chromium and ITO films where this gate bus line 3 cross the thin film transistor 10 and the drain bus lines 5, while it is constructed exclusively of the ITO film in other portions.
Ordinarily, five to seven sheets of photo-mask patterns are required in forming an inverted staggered type thin film transistor array. In accordance with the aforementioned method, however, it is possible to form a thin film field effect transistor array using only three sheets of photo-mask patterns.
Nonetheless, the wiring length will have to be increased as the area of the display becomes large, and the wiring width will have to be decreased as the display becomes highly fine-sized. As a result, the wiring resistance will be increased, which will cause the voltage applied to the gate bus line and the drain bus line to generate propagation delays in conjunction with the wiring capacitance. The propagation delay causes the application of the voltage to each of the thin film transistors to be insufficient and the addressing of the signal voltage to each of the pixels to be insufficient, bringing about a deterioration in the display quality. Particularly, the gate bus line is arranged along the horizontal direction, which is larger than the vertical one so that the wiring length thereof is large and the wiring resistance becomes high. In addition, the wiring capacitances such as capacitance where the gate bus line crosses the drain bus line and channel capacitance of the thin film transistor become large, so that the influence of the propagation delay on the gate bus line is larger than on the drain bus line. In the case of the thin film field effect transistor array obtained in accordance with the prior method described above, the greater part of the gate bus line is formed of transparent conductive ITO film with resistivity which is tens to several hundred times as large as that of a metal so that the wiring resistance is higher with correspondingly higher influence on the propagation delay.